Cirrus-logic CS42L73 Manuale Utente Scaricare il pdf (Pagina 67)

DS882F1 67

CS42L73

in “Audio ASRC Data In Lock” on page 124.

12. Start transmission of audio data to device.

13. Ramp up audio output.

• Unmute the analog volume for the headphone or line amplifiers.

• If digital soft-ramping is used, unmute the mixer path (setting mixer volume) and/or DAC digital vol-

ume.

• If no soft ramping is used, ramp up the analog and mixer volume to the desired level with however

many steps (control port writes) desired. This method (vs. using CS42L73’s soft-ramp features) al-

lows for potentially faster but more zipper-noise like volume ramp-ups or for ultraslow ramp ups with

equal-to (vs. analog soft-ramping) or coarser/noisier (vs. digital soft-ramping) steps.

4.12.3 Power-Down Sequence (xSP to HP/LO)

The power-down sequence must be used when the playback path is no longer needed and low power

consumption is desired and/or before calling the final power-down sequence.

1. To minimize pops on the headphone or line amplifier, according to the soft-ramping configuration:

• Analog soft ramping. Mute the analog outputs.

• Digital soft ramping. Mute the mixer path and/or DAC digital volume.

If either digital or analog soft ramping is being used, wait until the soft ramping to mute is completed

(refer to sections “Analog Output Soft Ramp” on page 96, “Digital Soft-Ramp” on page 96, and “Mix-

er Soft-Ramp Step Size/Period” on page 117 for ramp rate values that can be used to calculate the

ramp-to-mute time).

• No soft-ramping. Ramp the analog and/or digital volume down to the minimum level (maximum at-

tenuation) with however many steps (control port writes) as is desired.

through 54h)” on page 118, and/or HLx_DVOL

2. Power down the device.

3. Wait to allow the CS42L73’s circuits to finish powering down. The amount of time to wait depends on

which output path is being powered down.

HPOUT: 30 ms

EAR SPKOUT or LINEOUT: 50 ms

SPKOUT or SPKLINEOUT: 150 ms

4. Deactivate external xSP input signals.

5. Deactivate the MCLK signal first by using the MCLKDIS (if possible) and then by removing the

external source.

Note: The PDN and PDN_xx bits do not take effect if the MCLK signal is removed first.

6. If the device is to be completely powered down by removing the power supply rails, follow the

sequence specified in “Final Power-Down Sequence” on page 68. Otherwise, optionally bring RESET

low to achieve the lowest quiescent current. Note, by setting RESET

low, the Control Port register

values will return to their default states.

4.12.4 Recommended Sequence for Modification of the MCLK Signal

The CS42L73 requires the MCLK signal to be stable in frequency and uninterrupted whenever any sub-

blocks (PDN_xx) are powered up. When it is known there is going to be a change to the MCLK frequency

or that it will be stopping/starting, the following procedure should be executed.

1 2 ... 62 63 64 65 66 67 68 69 70 71 72 ... 138 139

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Cirrus-logic CS42L73 Manuale Utente Pagina 67

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