Cirrus-logic CS4341A Manuale Utente

1Copyright © Cirrus Logic, Inc. 2004(All Rights Reserved)Cirrus Logic, Inc.http://www.cirrus.comCS4341A24-Bit, 192 kHz Stereo DAC with Volume ControlF

CS4341A10 DS582F23.7 Popguard® Transient ControlThe CS4341A uses Popguard® technology to minimize the effects of output transients during power-upand

CS4341ADS582F2 113.9 Control Port InterfaceThe control port is used to load all the internal register settings (see section 5). The operation of the c

CS4341A12 DS582F23.9.3 I2C ModeIn the I2C mode, data is clocked into and out of the bi-directional serial control data line, SDA, bythe serial control

CS4341ADS582F2 133.9.3b I2C ReadTo read from the device, follow the procedure below while adhering to the control portSwitching Specifications.1) Init

CS4341A14 DS582F23.9.4 SPI ModeIn SPI mode, data is clocked into the serial control data line, CDIN, by the serial control port clock,CCLK (see Figure

CS4341ADS582F2 153.10 Memory Address Poi n t e r (M A P ) 3.10.1 INCR (AUTO MAP INCREMENT ENABLE)Default = ‘0’0 - Disabled1 - Enabled3.10.2 M

CS4341A16 DS582F24. REGISTER QUICK REFERENCEAddr Function 7 6 5 4 3 2 1 00h Mode Control 1 Reserved MC1 MC0 Reserved Reserved AUTOD MCLKDIV ReservedDE

CS4341ADS582F2 175. REGISTER DESCRIPTIONNOTE: All registers are read/write in I2C mode and write only in SPI mode, unless otherwise stated.5.1 MODE CO

CS4341A18 DS582F25.2.1 AUTO-MUTE (AMUTE) BIT 7 Default = 10 - Disabled1 - EnabledFunction:The Digital-to-Analog converter output will mute following

CS4341ADS582F2 195.2.4 POPGUARD® TRANSIENT CONTROL (POR) BIT 1 Default = 10 - Disabled1 - EnabledFunction:The PopGuard® Transient Control allows the

CS4341A2 DS582F2TABLE OF CONTENTS 1. PIN DESCRIPTION ...

CS4341A20 DS582F25.3.2 SOFT RAMP AND ZERO CROSS CONTROL (SZC) BIT 5-6 Default = 1000 - Immediate Changes01 - Changes On Zero Crossings10 - Soft Rampe

CS4341ADS582F2 21 01010 aL bL01011 aL b[(L+R)/2]0 1 1 0 0 a[(L+R)/2] MUTE0 1 1 0 1 a[(L+R)/2] bR0 1 1 1 0 a[(L+R)/2] bL0 1 1 1 1 a[(L+R)/2] b[(L+

CS4341A22 DS582F25.4 CHANNEL A VOLUME CONTROL (ADDRESS 03H)5.5 CHANNEL B VOLUME CONTROL (ADDRESS 04H)5.5.1 MUTE (MUTE) BIT 7 Default = 00 - Disabled1

CS4341ADS582F2 236. CHARACTERISTICS AND SPECIFICATIONS(Min/Max performance characteristics and specifications are guaranteed over the Specified Operat

CS4341A24 DS582F2ANALOG CHARACTERISTICS (CS4341A-KS) (Test conditions (unless otherwise specified): Input test signal is a 997 Hz sine wave at 0 dBFS;

CS4341ADS582F2 25ANALOG CHARACTERISTICS (CS4341A-KS) (Continued) Notes: 2. One-half LSB of triangular PDF dither is added to data.3. Refer to Figure

CS4341A26 DS582F2COMBINED INTERPOLATION & ON-CHIP ANALOG FILTER RESPONSE(The filter characteristics and the X-axis of the response plots have been

CS4341ADS582F2 27 Figure 10. Single-Speed Stopband Rejection Figure 11. Single-Speed Transition BandFigure 12. Single-Speed Transition Band

CS4341A28 DS582F2Figure 16. Double-Speed Transition Band (Detail) Figure 17. Double-Speed Passband Ripple

CS4341ADS582F2 29SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE 6. Only required for Quad-speed mode. Parameters Symbol Min Max

CS4341ADS582F2 33.10.1 INCR (Auto Map Increment Enable)... 153.10.2 MAP (Memo

CS4341A30 DS582F2SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (Inputs: Logic 0 = AGND, Logic 1 = VA)Notes: 7. Data must be held for sufficient ti

CS4341ADS582F2 31SWITCHING SPECIFICATIONS - CONTROL PORT INTERFACE (Continued)Notes: 9. tspi only needed before first falling edge of CS after RST ri

CS4341A32 DS582F2DC ELECTRICAL CHARACTERISTICS (AGND = 0 V; all voltages with respect to AGND.) DIGITAL INPUT CHARACTERISTICS (AGND = 0 V; all volta

CS4341ADS582F2 337. PARAMETER DEFINITIONSTotal Harmonic Distortion + Noise (THD+N)The ratio of the rms value of the signal to the rms sum of all other

CS4341A34 DS582F29. PACKAGE DIMENSIONSTHERMAL CHARACTERISTICS AND SPECIFICATIONS INCHES MILLIMETERSDIM MIN MAX MIN MAXA 0.053 0.069 1.35 1.75A1 0.004

CS4341A4 DS582F2LIST OF FIGURESFigure 1. Typical Connection Diagram ...

CS4341ADS582F2 51. PIN DESCRIPTION15214313416111610798125RST MUTEC SDIN AOUTASCLK VALRCK AGNDMCLK AOUTBSCL/CCLK REF_GND SDA/CDIN VQAD0/CSFILT+Pin

CS4341A6 DS582F22. TYPICAL CONNECTION DIAGRAM 13Serial AudioDataProcessorExternal ClockMCLKAGNDAOUTBCS4341ASDINLRCKVAAOUTA345140.1 µF+1µF12+3.3V or

CS4341ADS582F2 73. APPLICATIONS3.1 Upgrading from the CS4341 to the CS4341AThe CS4341A is pin and functionally compatible with all CS4341 designs, ope

CS4341A8 DS582F23.3 System ClockingThe device requires external generation of the master (MCLK), left/right (LRCK) and serial (SCLK)clocks. The LRCK,

CS4341ADS582F2 93.5 De-Emphasis ControlThe device includes on-chip digital de-emphasis. The Mode Control 2 bits select either the 32, 44.1, or 48kHz d