Cirrus-logic CS42L73 Manuale Utente Scaricare il pdf (Pagina 61)

DS882F1 61

CS42L73

4.10.2.4 DMIC Interface Clock Generation

Table 10 outlines the supported DMIC Interface Serial Clock (DMIC_SCLK) nominal frequencies and how

they are derived from the internal Master Clock (MCLK).

4.11 Digital Mixer

The digital mixer facilitates the mixing and routing of the CODEC’s inputs to its outputs. Figure 32. Digital

Mixer Diagram on page 62 illustrates the architecture and connectivity of the digital mixer.

Table 10. Digital Microphone Interface Clock Generation

MCLK Rate

(MHz)

Divide Ratio DMIC_SCLK

Rate (MHz)

DMIC_SCLK_DIV

Programming

5.6448 2 2.8224 0

41.4112 1

6.0000 2 3.0000 0

41.5000 1

6.1440 2 3.0720 0

41.5360 1

6.5000 2 3.2500 0

41.6250 1

6.4000 2 3.2000 0

41.6000 1

1 2 ... 56 57 58 59 60 61 62 63 64 65 66 ... 138 139

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Cirrus-logic CS42L73 Manuale Utente Pagina 61