Cirrus-logic CS42L73 Manuale Utente Scaricare il pdf (Pagina 57)

DS882F1 57

CS42L73

4.8.7 Mono/Stereo

Stereo/mono conversion is required whenever the number of channels for a serial port interface format

does not match the number of channels of the ASRC that connects the serial port to the digital mixer.

When the mono PCM format is configured on a port that has a stereo input ASRC, the mono input data

is automatically fanned-out by the CS42L73 to both ASRC channels. The XSP is the only serial port where

this configuration is possible.

When the stereo I²S format is configured on a port that has a mono input ASRC, one of the input channels

is selected by the user to be sent to the ASRC. The VSP is the only serial port where this configuration is

possible. The channel selection register bit is named V_SDIN_LOC.

When serial port that supports the stereo I²S format, naturally, a stereo ASRC will feed that port. If that

port also supports the mono PCM format, only one of the ASRC’s output channels will be transmitted

when PCM format is selected. In this case, the digital mixer must be configured to output a mono-mix of

its output to both stereo ASRC inputs that are destined for the serial port in question (for more information,

including programming instructions, refer to section “Mono and Stereo Paths” on page 63). The XSP and

VSP are the only serial ports where this configuration is possible.

4.8.8 Data Bit Depths

The CS42L73’s Serial Ports can transmit and receive up to 24 bits of audio data per sample. The number

of bits varies depending on the interface format selected and the clocking used.

4.8.8.1 I²S Format Bit Depths

The data word length of the I²S interface format (refer to section “I²S Format” on page 55) is ambiguous.

Fortunately, the I²S format also left justified, having a MSB-to-LSB bit ordering, which negates the need

for a word length control register. The following text describes how different bit depths are handled with

the I²S format.

Figure 30. PCM Format—Mode 2

xSP_LRCK

(WA)

xSP_SCLK

xSP_SDIN

16 bits

xSP_SDOUT

xSP_SCLK may stop or continue

MSB MSB-1 MSB-2 LSB +2 LSB +1 LSB

1/Fs

ext



16 xSP_SCLK periods

xSP_LRCK

(WA)

xSP_SCLK

xSP_SDIN

xSP_SDOUT

extra

= 0,

1/Fs

ext

= 16 xSP_SCLK periods

LSB

MSB

MSBLSB+1

extra

= 0 to N xSP_SCLK periods

(time between LSB and MSB data)

xSP_LRCK

(WA)

xSP_SCLK

xSP_SDIN

xSP_SDOUT

extra

= 1 xSP_SCLK period,

1/Fs

ext

= 17 xSP_SCLK periods

LSB MSBLSB+1

xSP_LRCK

(WA)

xSP_SCLK

xSP_SDIN

xSP_SDOUT

extra

= 2 xSP_SCLK periods,

1/Fs

ext

= 18 xSP_SCLK periods

LSB MSBLSB+1

xSP_SCLK may

stop or continue

Note:

x = X, A, or V

1 2 ... 52 53 54 55 56 57 58 59 60 61 62 ... 138 139

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Cirrus-logic CS42L73 Manuale Utente Pagina 57

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