Cirrus-logic CS42L73 Manuale Utente Pagina 56
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56 DS882F1
CS42L73
Mode 1:
– WA may be one or up to all-but-one xSP_SCLK periods wide
– 1st data bit is aligned to WA
Mode 2:
– WA may be one xSP_SCLK period wide
– 1st data bit follows WA
– Last data bit may be aligned to WA
Figure 28. PCM Format—Mode 0
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
16 bits
xSP_SDOUT
xSP_SCLK may stop or continue,
t
extra
= 0 to N xSP_SCLK periods
MSB MSB-1 MSB-2 MSB-3 LSB +2 LSB +1 LSB MSB
1/Fs
ext
17 xSP_SCLK periods when WA is 1 xSP_SCLK period wide,
18 xSP_SCLK periods when WA is 2 xSP_SCLK periods wide
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
xSP_SDOUT
MSB
t
extra
= 0,
WA is 1 xSP_SCLK period wide,
1/Fs
ext
= 17 xSP_SCLK periods
LSB
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
xSP_SDOUT
MSB
t
extra
= 0,
WA is 2 xSP_SCLK periods wide,
1/Fs
ext
= 18 xSP_SCLK periods
LSB
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
xSP_SDOUT
MSB
t
extra
= 1 xSP_SCLK period,
WA is 1 xSP_SCLK period wide,
1/Fs
ext
= 18 xSP_SCLK periods
LSB
PCM_SCLK may
stop or continue
MSB-1 MSB-2 MSB-3 LSB+2 LSB+1 LSB
LSB MSB
MSB MSB MSBMSB
Note:
x = X, A, or V
Figure 29. PCM Format—Mode 1
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
16 bits
xSP_SDOUT
xSP_SCLK may stop or continue
MSB MSB-1 MSB-2 MSB-3 LSB+2 LSB+1 LSB MSB
1/Fs
ext
16 xSP_SCLK periods
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
xSP_SDOUT
MSB-1
t
extra
= 0,
1/Fs
ext
= 16 xSP_SCLK periods
LSB
MSB-1
WA may be one or up to all-but-one xSP_SCLK periods wide
MSBLSB+1
t
extra
= 0 to N xSP_SCLK periods
(time between LSB and MSB data)
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
xSP_SDOUT
MSB-1
t
extra
= 1 xSP_SCLK period,
1/Fs
ext
= 17 xSP_SCLK periods
LSB MSBLSB+1
xSP_LRCK
(WA)
xSP_SCLK
xSP_SDIN
xSP_SDOUT
MSB-1
t
extra
= 2 xSP_SCLK periods,
1/Fs
ext
= 18 xSP_SCLK periods
LSB MSBLSB+1
xSP_SCLK may
stop or continue
Note:
x = X, A, or V
- Product Overview 1
- Ultralow Power Consumption 1
- Applications 1
- System Features 1
- General Description 3
- TABLE OF CONTENTS 4
- LIST OF FIGURES 9
- LIST OF TABLES 10
- 12 DS882F1 12
- DS882F1 13 13
- 1.3 Pin/Ball Descriptions 14
- DS882F1 15 15
- 2. TYPICAL CONNECTION DIAGRAM 17
- ABSOLUTE MAXIMUM RATINGS 20
- DC ELECTRICAL CHARACTERISTICS 21
- 22 DS882F1 22
- CHARACTERISTICS 24
- MIC BIAS CHARACTERISTICS 26
- --70-60dB 27
- 0.73•VA 0.79•VA 0.85•VA V 27
- Test Load 28
- Measurement 28
- FILTER CHARACTERISTICS 33
- POWER CONSUMPTION 34
- DMIC_SCLK 37
- = “s” or “m” 38
- Repeated 40
- 4. APPLICATIONS 41
- 4.5 Class H Amplifier 44
- 4.5.1 Power Control Options 44
- 48 DS882F1 48
- 4.5.3 Efficiency 49
- 4.6 DAC Limiter 49
- LIMRRATEx[2:0] 50
- LIMARATEx[2:0] 50
- 4.8 Serial Ports 51
- 4.8.1 Power Management 51
- 4.8.2 I/O 51
- 4.8.3 High-impedance Mode 52
- 4.8.4 Master and Slave Timing 52
- 4.8.4.1 SCLK = MCLK Modes 53
- 4.8.6 Formats 54
- 4.8.6.1 I²S Format 55
- 4.8.6.2 PCM Format 55
- 4.8.7 Mono/Stereo 57
- 4.8.8 Data Bit Depths 57
- 4.8.8.1 I²S Format Bit Depths 57
- 4.8.8.2 PCM Format Bit Depths 58
- 4.10 Input Paths 59
- DMIC_CLK 60
- 4.11 Digital Mixer 61
- 62 DS882F1 62
- 4.11.1 Mono and Stereo Paths 63
- 4.15 Interrupts 70
- 4.16 Control Port Operation 71
- 4.16.1 I²C Control 71
- 7 6 5 4 3 2 1 0 72
- 4.17 Fast Start Mode 73
- SPKLINEOUT 74
- EARSPKOUT 74
- Normal audioNo audio 75
- Clipped/Ramping audio 75
- 5. REGISTER QUICK REFERENCE 76
- DS882F1 77 77
- 78 DS882F1 78
- DS882F1 79 79
- 80 DS882F1 80
- (Read Only) 80
- 6. REGISTER DESCRIPTION 81
- 6.12.2 ASP Sample Rate 90
- 6.13.1 ASP Master/Slave Mode 90
- 6.14.5 VSP SDIN Location 92
- 6.15.1 VSP Master/Slave Mode 92
- 6.16.1 VSP Sample Rate 93
- 6.16.2 XSP Sample Rate 93
- 6.17.1 Digital Swap/Mono 94
- 6.17.2 Input Path Channel B=A 94
- 6.17.4 PGA Soft-Ramp 95
- 6.17.5 Analog Zero Cross 95
- 6.17.6 Digital Soft-Ramp 96
- 6.19.1 Mic PREAMP x Volume 98
- 6.19.2 PGAx Volume 98
- DS882F1 99 99
- DS882F1 103 103
- 104 DS882F1 104
- 76543210 110
- (Address 2Eh) 112
- 6.44.3 ALCx Soft-Ramp Disable 116
- 6.45.3 Mixer Soft-Ramp Enable 117
- 118 DS882F1 118
- DS882F1 119 119
- 120 DS882F1 120
- DS882F1 121 121
- 7. PCB LAYOUT CONSIDERATIONS 125
- 8. PERFORMANCE DATA 126
- DS882F1 127 127
- 128 DS882F1 128
- 8.3 Core Circuitry Attributes 129
- 8.3.1 ASRC Attributes 129
- 8.3.1.1 Response 129
- 8.3.1.2 Group Delay 130
- 8.3.1.3 Lock Time 130
- DS882F1 131 131
- 8.4.2 DAC HPF Response 132
- 8.4.4 Startup Times 133
- 9. PARAMETER DEFINITIONS 134
- 10.PACKAGE DIMENSIONS 135
- BUMP SIDESIDE VIEW 136
- TOP SIDE 136
- 11.THERMAL CHARACTERISTICS 137
- 12.ORDERING INFORMATION 137
- 13.REFERENCES 137
- 14.REVISION HISTORY 138
- DS882F1 139 139
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