Cirrus-logic CS4354 Manuale Utente

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Copyright Cirrus Logic, Inc. 2011
(All Rights Reserved)
http://www.cirrus.com
5-V Stereo DAC with 2-V
RMS
Ground-Centered Output
Features
Advanced multibit delta–sigma modulator
101 dB A-weighted dynamic range
–86 dB THD+N
Single-ended ground-centered analog
architecture
No DC-blocking capacitors required
Integrated inverting charge pump
Filtered line-level outputs
–2V
RMS
full-scale output
Low-latency digital filtering
Supports sample rates up to 192 kHz
24-bit I²S input
+5-V analog supply with integrated inverting
charge pump and regulator for core logic, and
+1.8-V to +5-V interface power supplies
50-mW power consumption
14-pin SOIC, lead-free assembly
Description
The CS4354 is a complete stereo digital-to-analog sys-
tem including digital interpolation, third-order multi-bit
delta–sigma digital-to-analog conversion, digital de-em-
phasis, analog filtering, and on-chip 2 V
RMS
line-level
driver from a 5 V supply.
The advantages of this architecture include ideal differ-
ential linearity, no distortion mechanisms due to resistor
matching errors, no linearity drift over time and temper-
ature, high tolerance to clock jitter, and a minimal set of
external components.
These features are ideal for cost-sensitive, two-channel
audio systems including video game consoles, Blu-Ray
Disc
®
and DVD players, set-top boxes, digital TVs, and
DAB/DMB devices.
The CS4354 is available in a 14-pin SOIC package in
Commercial (–40°C to +85°C) grade. The CDB4354
Customer Demonstration Board is also available for de-
vice evaluation and implementation suggestions.
Please see “Ordering Information” on page 23 for com-
plete details.
PCM Serial
Audio Port
Level Shifter
I²S Serial
Audio Input
Multibit
Modulator
Interpolation
Filters + HPF
Left Channel
Right Channel
Power-On
Reset
Auto Speed
Mode Detect
Analog Supply (VA)
+5 V
Inverting
Charge
Pump
1.8V reg
-VA
Interface Supply (VL)
+1.8V to +5V
Ground-Centered,
2 Vrms Line Level
Outputs
DAC
Sept '11
DS895F2
CS4354
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Sommario

Pagina 1 - Ground-Centered Output

Copyright  Cirrus Logic, Inc. 2011 (All Rights Reserved)http://www.cirrus.com5-V Stereo DAC with 2-VRMS Ground-Centered OutputFeatures Advanced mult

Pagina 2 - LIST OF FIGURES

10 DS895F2CS4354DIGITAL INTERFACE CHARACTERISTICSTest conditions (unless otherwise specified): GND = 0 V; all voltages with respect to ground.INTERNAL

Pagina 3 - LIST OF TABLES

DS895F2 11CS4354DC ELECTRICAL CHARACTERISTICSTest conditions (unless otherwise specified): VA = 5 V, VL = 3.3 V; GND = 0 V; SDIN = 0; all voltages wit

Pagina 4 - 1. PIN DESCRIPTIONS

12 DS895F2CS43543. TYPICAL CONNECTION DIAGRAMVL+1.8 V to +5 VLRCKMCLKSCLK/DEMSDIN-VFILTAOUTAVA470 2.2 nFRextRextLine Level OutLeft & RightDigital

Pagina 5 - ABSOLUTE MAXIMUM RATINGS

DS895F2 13CS43544. APPLICATIONS4.1 Ground-Centered Line OutputsAn on-chip charge pump creates a negative supply which allows the full-scale output swi

Pagina 6 - DAC ANALOG CHARACTERISTICS

14 DS895F2CS43544.4 Serial ClockThe serial clock controls the shifting of data into the input data buffers. The CS4354 supports both externaland inter

Pagina 7

DS895F2 15CS4354Figure 7. De-Emphasis Curve, Fs = 44.1 kHzNote: De-emphasis is only available in Single-Speed Mode.4.5 Internal High-Pass FilterThe C

Pagina 8

16 DS895F2CS4354When power is first applied, the POR circuit monitors the VA supply voltage to determine when it reachesa defined threshold, Von1. At

Pagina 9 - DS895F2 9

DS895F2 17CS4354USER: Apply PowerUSER: Apply MCLKMCLK/LRCK Ratio DetectionUSER: Apply LRCKPower-On Reset StatePower-Down StateInitialization StatePowe

Pagina 10 - (internal)

18 DS895F2CS43544.9 Recommended Operational SequencesThe following sequences are recommended for minimal pops and clicks when transitioning between di

Pagina 11 - DC ELECTRICAL CHARACTERISTICS

DS895F2 19CS4354shows the recommended power arrangements with VA and VL connected to clean supplies. It is stronglyrecommended that a single ground pl

Pagina 12 - 3. TYPICAL CONNECTION DIAGRAM

2 DS895F2CS4354TABLE OF CONTENTS1. PIN DESCRIPTIONS ...

Pagina 13 - 4. APPLICATIONS

20 DS895F2CS43545. COMBINED DIGITAL AND ON-CHIP ANALOG FILTER RESPONSE PLOTS 0.4 0.5 0.6 0.7 0.8 0.91−120−100−80−60−40−200Single−Speed Stopband Re

Pagina 14 - 4.4.2.1 De-Emphasis Control

DS895F2 21CS43540.45 0.46 0.47 0.48 0.49 0.5 0.51 0.52 0.53 0.54 0.55−10−9−8−7−6−5−4−3−2−10Double−Speed Transition Band DetailFrequency(normalized to

Pagina 15 - 4.5 Internal High-Pass Filter

22 DS895F2CS43546. PARAMETER DEFINITIONSDynamic RangeThe ratio of the full-scale RMS value of the signal to the RMS sum of all other spectral componen

Pagina 16 - 4.8 Initialization

DS895F2 23CS43547. PACKAGE INFORMATION7.1 Dimensions 7.2 Thermal Characteristics 8. ORDERING INFORMATIONINCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA

Pagina 17 - DS895F2 17

24 DS895F2CS43549. REVISION HISTORY Release ChangesF1 Changed 1.8 V VL  5.0 V to 1.8 V VL  5.0 V for both high- and low-level input voltage para

Pagina 18 - 4.9.3 Sample Rate Change

DS895F2 3CS4354Figure 14. Double-Speed Stopband Rejection ... 2

Pagina 19 - 4.10.1 Capacitor Placement

4 DS895F2CS43541. PIN DESCRIPTIONS Pin Name Pin # Pin DescriptionVL 1 Serial Audio Interface Power (Input) - Positive power for the serial audio int

Pagina 20 - 20 DS895F2

DS895F2 5CS43542. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONSGND = 0 V; all voltages with respect to ground.(Note 1)Notes: 1.

Pagina 21 - DS895F2 21

6 DS895F2CS4354DAC ANALOG CHARACTERISTICSTest conditions (unless otherwise specified): TA = 25 °C; VA = 5 V, VL = 3.3 V; GND = 0 V; FILT+, -VFILT, and

Pagina 22 - 6. PARAMETER DEFINITIONS

DS895F2 7CS4354COMBINED DIGITAL AND ON-CHIP ANALOG FILTER CHARACTERISTICSThe filter characteristics have been normalized to the sample rate (Fs) and c

Pagina 23 - 8. ORDERING INFORMATION

8 DS895F2CS4354SWITCHING SPECIFICATIONS - SERIAL AUDIO INTERFACE 12. Not all sample rates are supported for all clock ratios. See Section 4.2 “Sample

Pagina 24 - 9. REVISION HISTORY

DS895F2 9CS4354Figure 1. External Serial Clock Mode Input TimingFigure 2. Internal Serial Clock Mode Input TimingFigure 3. Internal Serial Clock Ge

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