Cirrus-logic CS4228A Manuale Utente

1Copyright  Cirrus Logic, Inc. 2003(All Rights Reserved)www.cirrus.comCS4228A24-Bit, 96 kHz Surround Sound CodecFeatures! Six 24-bit D/A converters-

CS4228A10SWITCHING CHARACTERISTICS - CONTROL PORT (Inputs: Logic 0 = 0V, Logic 1 = VL)Notes: 18. Data must be held for sufficient time to bridge the t

CS4228A11SWITCHING CHARACTERISTICS - CONTROL PORT (Inputs: Logic 0 = 0V, Logic 1 = VL)Notes: 20. Data must be held for sufficient time to bridge the 3

CS4228A122. TYPICAL CONNECTION DIAGRAM+5VSupply+1µF 0.1µF+1µF0.1µFVA VDAGND DGNDMCLKExternal Clock InputNote : MCLK Logic High is VLAll unused logic i

CS4228A133. FUNCTIONAL DESCRIPTION3.1 OverviewThe CS4228A is a 24-bit audio codec comprised of2 analog-to-digital converters (ADC) and 6 digital-to-an

CS4228A14The high pass filters can be disabled by setting theHPF bit in the ADC Control register. When assert-ed, any DC present at the analog inputs

CS4228A15returns to the attenuation level set in the DigitalVolume Control register. The attenuation isramped up and down at the rate specified by the

CS4228A16channels of DAC data is input on SDIN1 and thestereo ADC data is output on SDOUT. Table 1 out-lines the serial port input to DAC channelalloc

CS4228A17LRCKSCLKLeft ChannelRight Channel654321098715 14 13 12 11 10654321098715 14 13 12 11 10SDINxFigure 12. Right Justified Serial Audio FormatsRi

CS4228A183.7 Control Port SignalsInternal registers are accessed through the controlport. The control port may be operated asynchro-nously with respec

CS4228A19Since the read operation can not set the MAP, anaborted write operation is used as a preamble. Asshown in Figure 16, the write operation is a

CS4228A2TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ... 4SPECIFIED OPE

CS4228A20The CS4228A will enter a stand-by mode if themaster clock source stops for approximately 10 µsor if the number of MCLK cycles per LRCK period

CS4228A214. REGISTER QUICK REFERENCEAddr Function 7 6 5 4 3 2 1 0MAP Memory AddressPointerINCR Reserved Reserved MAP4 MAP3 MAP2 MAP1 MAP01000 0 0 0 10

CS4228A225. REGISTER DESCRIPTIONSAll registers are read/write except for Chip Status, which is read only. See the following bit definition tablesfor b

CS4228A23DACPDN12 Power down the analog section of DAC 1 and 2*0 - Normal1 - Power down DAC 1 and 2.DACPDN34 Power down the analog section of DAC 3 an

CS4228A245.6 DAC Mute2 ControlAddress 0x05MUTEC Controls the MUTECpin0 - Normal operation*1 - MUTECpin asserted lowMUTCZ Automatically asserts the MUT

CS4228A255.9 Serial Port ModeAddress 0x0DDCK1:0 Sets the number of Serial Clocks (SCLK) per Fs period (LRCLK)DMS1:0 Sets the master/slave mode of the

CS4228A266. PIN DESCRIPTIONSDIN1, SDIN2,SDIN31, 2, 3 Serial Audio Data In (Input) - Two's complement MSB-first serial audio data is input on this

CS4228A27LRCK 6 Left/Right Clock (Bidirectional) - The Left/Right clock determines which channel is cur-rently being input or output on the serial aud

CS4228A28AINR+, AINR-,AINL+, AINL-16, 17, 19, 20 Differential Analog Inputs (Input) - The analog signal inputs are presented differentially tothe modu

CS4228A297. PARAMETER DEFINITIONSDynamic RangeThe ratio of the full scale RMS value of the signal to the RMS sum of all other spectralcomponents over

CS4228A33.7 Control Port Signals ... 183.7.1 SPI

CS4228A30Gain ErrorThe deviation from the nominal full scale output for a full scale input.Gain DriftThe change in gain value with temperature. Units

CS4228A318. PACKAGE DIMENSIONSNotes: 1.“D” and “E1” are reference datums and do not included mold flash or protrusions, but do include moldmismatch an

CS4228A41. CHARACTERISTICS AND SPECIFICATIONS(Min/Max performance characteristics and specifications are guaranteed over the Specified Operating Condi

CS4228A5ANALOG CHARACTERISTICS (Test conditions (unless otherwise specified): Input test signal is a997 Hz sine wave at 0 dBFS; measurement bandwidth

CS4228A6ANALOG CHARACTERISTICS (Continued)8. The passband and stopband edges scale with frequency. For input word rates, Fs, other than 44.1 kHz,the 0

CS4228A7POWER AND THERMAL CHARACTERISTICSNotes: 11. Current consumption increases with increasing FS and increasing MCLK. Variance between speedmodesi

CS4228A8SWITCHING CHARACTERISTICS (Inputs: Logic 0 = 0V, Logic 1 = VL)Notes: 14. See Cl1:0 register on page 22 for settings.15. After powering up the

CS4228A9Figure 1. Serial Audio Port Master Mode TimingtmslrSCLK(o u tp u t)LRCK(o u tp u t)SDOUTsckhscklttMSBMSB-1tdpdSDOUTLRCK(input)SCLK(input)SDIN1