Cirrus-logic CS4234 Manuale Utente

Copyright  Cirrus Logic, Inc. 2012 (All Rights Reserved)http://www.cirrus.com4 In/5 Out CODEC with Programmable Class H ControllerDAC Features Advan

DS899F1 10CS4234DC ELECTRICAL CHARACTERISTICS GND = 0 V; all voltages with respect to ground. Notes:7. No external loads should be connected to the V

DS899F1 11CS4234TYPICAL CURRENT CONSUMPTIONThis table represents the power consumption for individual circuit blocks within the CS4234. CS4234 is conf

DS899F1 12CS4234 ANALOG INPUT CHARACTERISTICSTest Conditions (unless otherwise specified): Device configured as shown in Figure 2 on page 8. Input sin

DS899F1 13CS4234 100 k4.7 uF100 k100 k470 pF634 90 .9 Analog Signal ++-100 k4.7 uF100 k100 k470 pF634 90 .9 Analog Signal -+-VAVA2700

DS899F1 14CS4234ADC DIGITAL FILTER CHARACTERISTICSTest Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 8. In

DS899F1 15CS4234ANALOG OUTPUT CHARACTERISTICSTest Conditions (unless otherwise specified): Device configured as shown in Section 2. on page 8. VA_SEL

DS899F1 16CS4234COMBINED DAC INTERPOLATION AND ON-CHIP ANALOG FILTER RESPONSETest Conditions (unless otherwise specified): VA_SEL = 0 for VA = 3.3 VDC

DS899F1 17CS4234DIGITAL I/O CHARACTERISTICSParameters Symbol Min Typ Max UnitsHigh-Level Input Voltage (all input pins except RST)(% of VL)(VL=1.8V)V

DS899F1 18CS4234SWITCHING CHARACTERISTICS - SERIAL AUDIO INTERFACEVA_SEL = 0 for VA = 3.3 VDC, 1 for VA = 5.0 VDC.Notes:26. After applying power to th

DS899F1 19CS4234Figure 6. TDM Serial Audio Interface Timing SDOUT1(output )SDINx(input )tdsSCLK(input )FS/LRCK(input )MSBtdh1MSB-1tlckstdh2MSB MSB-1t

DS899F1 2CS4234General DescriptionThe CS4234 is a highly versatile CODEC that combines 4 channels of high performance analog to digital conver-sion, 4

DS899F1 20CS4234SWITCHING SPECIFICATIONS - CONTROL PORTTest conditions (unless otherwise specified): Inputs: Logic 0 = GND = 0 V, Logic 1 = VL; SDA lo

DS899F1 21CS42344. APPLICATIONS4.1 Power Supply Decoupling, Grounding, and PCB LayoutAs with any high-resolution converter, the CS4234 requires carefu

DS899F1 22CS42344.2.2 Power-downTo prevent audio transients at power-down, the DC-blocking capacitors must fully discharge before turn-ing off the pow

DS899F1 23CS4234 Figure 9. System Level Initialization and Power-up / Power-down SequenceSystem OperationalSystem UnpoweredDAC1-4 Fully OperationalAD

DS899F1 24CS42344.2.3 DAC DC LoadingFigure 10 shows the analog output configuration during power-up, with the AOUTx± pins clamped to VQto prevent pops

DS899F1 25CS42344.3 I²C Control PortAll device configuration is achieved via the I²C control port registers as described in the Switching Specifi-cati

DS899F1 26CS4234Receive acknowledge bit.Send stop condition, aborting write. Send start condition. Send 0010xxx1 (chip address and read operation). Re

DS899F1 27CS4234 Note:34. 128x and 192x ratios valid only in Left Justified or I²S formats.4.4.2 Master Mode Clock RatiosAs a clock master, FS/LRCK an

DS899F1 28CS4234The serial bit clock, SCLK, must be synchronously derived from the master clock, MCLK, and be equal to512x, 256x, 128x, 64x, 48x or 32

DS899F1 29CS4234The structure in which the serial data is coded into the TDM slots is shown in Figure 16. When using a48 kHz sample rate with a 24.576

DS899F1 3CS4234TABLE OF CONTENTS1. PIN DESCRIPTIONS ...

DS899F1 30CS4234 SDIN1Input Data 1.1.A [31:8]Input Data 1.1.B [7:0]Input Data 1.2.A [31:8]Input Data 1.2.B [7:0]Input Data 1.3

DS899F1 31CS42344.5.2 Left Justified and I²S ModesThe serial port of the CS4234 supports the Left Justified and I²S interface formats with valid bit d

DS899F1 32CS42344.6 Internal Signal Path The CS4234 device includes four main paths in which audio data can be routed. The analog input path,shown in

DS899F1 33CS42344.6.1.2 DAC1-4, DAC5, and Low-latency Signal RoutingIn TDM mode, each of the 3 output paths have a collection of bits that advise the

DS899F1 34CS4234SDIN1SDIN2MCL K = 12.288/24.576MHzFS/LRCK = 48/96kHzSCLK = 12.288/24.576MHz Slot 1 [31:0] Slot 2 [31:0] Slot 3 [31:0] Slot 4 [31:0]

DS899F1 35CS4234Figure 22. Example Serial Data Source SelectionSDIN1SDIN2DAC3 [23:0] DAC5 [7:0] DAC4 [23:0] xDAC1 [23:0] DAC5 [23:16] DAC2 [23:0] DAC

DS899F1 36CS4234As can be seen from Figure 22, setting ‘100’ of the DAC5 Source[2:0] bits configures the DAC5 path touse the mask bits to determine wh

DS899F1 37CS4234Table 7. Unmasking SDIN2 Data from DAC5 PathDue to the flexibility of the DAC5 path, it is possible to errantly unmask several data sl

DS899F1 38CS42344.6.2 ADC Path 4.6.2.1 Analog InputsAINx+ and AINx- are line-level differential analog inputs. The analog input pins do not self-bia

DS899F1 39CS42344.6.3 DAC1-4 Path The AOUT1-4 signals are driven by the data placed into the DAC1-4 path. This data can be placed intothe DAC1-4 pat

DS899F1 4CS42346.25 Interrupt Notification 2 (Address 22h) (Read Only) ... 697. ADC

DS899F1 40CS4234The de-emphasis feature is included to accommodate audio recordings that utilize 50/15 s preemphasisequalization as a means of noise

DS899F1 41CS42344.6.5 DAC5 PathThe 5th DAC in the CS4234 is a fully functional audio-grade DAC with performance specifications identicalto that of the

DS899F1 42CS42344.6.5.2 Generating the Tracking Signal Inside an External DSPIf the tracking signal is to be generated within an external DSP, the tra

DS899F1 43CS4234control and other associated peripheries for DAC1-4 is shown in Figure 28 below. The implementation de-tails for the volume control an

DS899F1 44CS42344.6.6.2 Soft RampThe CS4234 soft ramp feature (enabled using the DAC1-4 ATT. and DAC5 ATT. bits) is activated on muteand unmute transi

DS899F1 45CS4234Two control parameters allow the user to limit the ramp-rate range to achieve optimum effect. The MINDELAY[2:0] setting limits the max

DS899F1 46CS4234Table 8. Soft Ramp RatesFull-scale ramp is 96 dB (-90 dB to +6 dB)4.6.6.3 Noise GateThe CS4234 is equipped with a Noise Gate feature t

DS899F1 47CS42344.7 Reset LineThe reset line of the CS4234 is used to place the device into a reset condition. In this condition, all of thevalues of

DS899F1 48CS4234gardless of the setting of the mask bit. Setting the mask bit only prevents the interrupt pin from beingflagged upon the occurrence.4.

DS899F1 49CS4234USER: Mask bit(s) set to 0Unmasked error occursStatus Register bit changes to ‘1’ and INT pin set to active levelUSER: Read Status Re

DS899F1 5CS4234Figure 41. SSM DAC Passband Ripple ...

DS899F1 50CS42345. REGISTER QUICK REFERENCEDefault values are shown below the bit names.AD Function 7 6 5 4 3 2 1 0 (Read Only Bits are shown in Ita

DS899F1 51CS423416h VolumeMode MUTE DELAY[1:0] MIN DELAY[2:0] MAX DELAY[2:0] p651 0 0 0 0 1 1 1 17h MasterVolume MASTER VOLUME[7:0] p660 0 0 1 0

DS899F1 52CS42346. REGISTER DESCRIPTIONSAll registers are read/write unless otherwise stated. All “Reserved” bits must maintain their default state. D

DS899F1 53CS42346.3 Clock and SP Select (Address 06h)6.3.1 Base Rate AdvisoryAdvises the CS4234 of the base rate of the incoming base rate. This allow

DS899F1 54CS42346.4 Sample Width Select (Address 07h)6.4.1 Output Sample WidthThese bits set the width of the samples placed into the outgoing SDOUTx

DS899F1 55CS42346.5 Serial Port Control (Address 08h)6.5.1 Invert SCLKWhen set, this bit inverts the polarity of the SCLK signal.6.5.2 DAC5 Input Sour

DS899F1 56CS42346.6 Serial Port Data Select (Address 09h)6.6.1 DAC1-4 Data SourceSets which portion of data is to be routed to the DAC1-4 data paths.6

DS899F1 57CS42346.7 Serial Data Input 1 Mask 1 (Address 0Ah)6.7.1 SDIN1 Mask 1This field determines what data is masked from the max detect and envelo

DS899F1 58CS42346.9 Serial Data Input 2 Mask 1 (Address 0Ch)6.9.1 SDIN2 Mask 1This field determines what data is masked from the max detect and envelo

DS899F1 59CS42346.11 Tracking Power Supply Control (Address 0Eh)6.11.1 Tracking Power Supply ModeIf DAC5 FLTR (Section 6.15.5) is set to Tracking Powe

DS899F1 6CS42341. PIN DESCRIPTIONS Figure 1. CS4234 PinoutPin Name Pin # Pin DescriptionSDA 1Serial Control Data (Input/Output) - Bidirectional data

DS899F1 60CS42346.11.3 Group DelaySets the group delay added to the DAC1-4 path. This delay is in addition to any inherent delay in the DAC.Modify the

DS899F1 61CS42346.13 ADC Control 2 (Address 10h)6.13.1 Mute ADCxMutes the ADCx signal6.13.2 Power Down ADCxPowers down the ADCx path.6.14 Low Latency

DS899F1 62CS42346.15 DAC Control 1 (Address 12h)6.15.1 DAC1-4 Noise GateThis sets the bit depth at which the Noise Gate feature should engage for the

DS899F1 63CS42346.15.5 DAC5 Configuration and Filter SelectionSelects the filtering applied to the DAC5 data or configures the DAC5 Path used to gener

DS899F1 64CS42346.17.2 DAC1-4 AttenuationSets the mode of attenuation used for the DAC1-4 path.Note: See Section 4.6.6 Volume Control for details rega

DS899F1 65CS42346.19 Volume Mode (Address 16h)6.19.1 Mute DelaySets the delay between the volume steps during the muting and unmuting of a signal when

DS899F1 66CS42346.20 Master and DAC1-5 Volume Control (Address 17h, 18h, 19h, 1Ah, 1Bh, and 1Ch)6.20.1 x Volume ControlSets the level of the x Volume

DS899F1 67CS42346.22 Interrupt Mask 1 (Address 1Fh)6.22.1 Test Mode Error Interrupt MaskAllows or prevents a Test Mode Error event from flagging the i

DS899F1 68CS42346.23 Interrupt Mask 2 (Address 20h)6.23.1 DACx Clip Interrupt MaskAllows or prevents a DACx Clip event from flagging the interrupt pin

DS899F1 69CS42346.25 Interrupt Notification 2 (Address 22h) (Read Only)6.25.1 DACx Clip A DACx Clip occurred since the last clearing of the Interrupt

DS899F1 7CS42341.1 I/O Pin CharacteristicsInput and output levels and associated power supply voltage are shown in the table below. Logic levelsshould

DS899F1 70CS42347. ADC FILTER PLOTS0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1−100−90−80−70−60−50−40−30−20−100Frequency (normalized to Fs)Amplitude (dB)St

DS899F1 71CS42348. DAC FILTER PLOTSFigure 38. SSM DAC Stopband Rejection Figure 39. SSM DAC Transition BandFigure 40. SSM DAC Transition Band (Deta

DS899F1 72CS4234Figure 42. DSM DAC Stopband Rejection Figure 43. DSM DAC Transition BandFigure 44. DSM DAC Transition Band (Detail)Figure 45. DSM

DS899F1 73CS42349. PACKAGE DIMENSIONS Figure 46. Package DrawingNotes: 1. Dimensioning and tolerance per ASME Y4.5M - 1994.2. Dimensioning lead width

DS899F1 74CS423410.ORDERING INFORMATION11.APPENDIX A: INTERNAL TRACKING POWER SUPPLY SIGNALThe tracking signal for a Class H amplifier tracks the enve

DS899F1 75CS4234Signal Color Key:Signal Coming into the BlockSignal Going out of the BlockEnvelope of Abs. Max0VMode SelectGain / Volu meInterpo latio

DS899F1 76CS423411.1 Voltage HeadroomHeadroom is another word for the static DC offset inserted into the tracking signal. This offset allows the railv

DS899F1 77CS423411.3.1 SMPS Voltage Conversion Gain (K2)The gain of the SMPS voltage conversion, in units of V/V, can be determined by dividing the ma

DS899F1 78CS42340V0VVA/2VA/2VA/2Digital "0"Digital "0"Digital "0"Full ScaleFull ScaleFull Scale0V0.5xFull Scale0.5xFull

DS899F1 79CS423412.REVISION HISTORYRelease ChangesF1 – Added left justified and I2S serial ports to system features on front page. – Renamed the FS pi

DS899F1 8CS42342. TYPICAL CONNECTION DIAGRAM CS4234AIN 4-AIN 3+AIN 2-AIN 3-VAFILT +AIN 1+AIN 1-AIN 2+AIN 4+SDOUT1VLGNDFS/LRCKMCLKSDIN2SDIN1SDAVDREGS

DS899F1 9CS42343. CHARACTERISTICS AND SPECIFICATIONSRECOMMENDED OPERATING CONDITIONSGND = 0 V; all voltages with respect to ground. (Note 3)Notes: 3.