Cirrus-logic CS4361 Manuale Utente Scaricare il pdf (Pagina 10)

CS4361

Confidential Draft

9/30/11

sclkh

slrs

slrd

sdlrs

sdh

sclkl

SDATA

SCLK

LRCK

Figure 3. External Serial Mode Input Timing

SDATA

*INTERNAL SCLK

LRCK

sclkw

sdlrs

sdh

sclkr

Figure 4. Internal Serial Mode Input Timing

* The SCLK pulses shown are internal to the CS4361.

SDATA

LRCK

MCLK

*INTERNAL SCLK

Figure 5. Internal Serial Clock Generation

* The SCLK pulses shown are internal to the CS4361.

N equals MCLK divided by SCLK

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Cirrus-logic CS4361 Manuale Utente Pagina 10