Cirrus-logic CS5372A Manuale Utente Scaricare il pdf (Pagina 11)

CS5371A CS5372A

DS748F3 11

DIGITAL CHARACTERISTICS (CONT.)

MCLK

MSYNC

t

MDATA

TDATA

0

(2.048 MHz)

(512 kHz)

(256 kHz)

SYNC

MFLAG

Figure 6. System Timing Diagram

MCLK

MSYNC

t

0

(2.048 MHz)

t

mss

t

mcl k

t

msync

t

msh

MDATA

(512 kHz)

MFLAG

t

mdata

Figure 7. MCLK / MSYNC Timing Detail

1 2 ... 6 7 8 9 10 11 12 13 14 15 16 ... 31 32

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