Cirrus-logic CS5372A Manuale Utente

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Copyright Cirrus Logic, Inc. 2010
(All Rights Reserved)
http://www.cirrus.com
CS5371A
CS5372A
Low-power, High-performance
ΔΣ
Modulators
Features
Fourth-order ΔΣ Architecture
Clock-jitter-tolerant Architecture
Input Voltage: 5 V
pp
Fully Differential
Input Signal Bandwidth: DC to 2 kHz
High Dynamic Range
127 dB SNR @ 215 Hz BW (2 ms sampling)
124 dB SNR @ 430 Hz BW (1 ms sampling)
Low Total Harmonic Distortion
-118 dB THD typical (0.000126%)
Low Power Consumption
Normal operation: 25 mW per channel
Power down: 10 µW per channel
Small Footprint, 24-pin SSOP package
Multi-channel System Support
1-channel System: CS5371A
2-channel System: CS5372A
3-channel System: CS5371A + CS5372A
4-channel System: CS5372A + CS5372A
Bipolar Power Supply Configuration
VA+ = +2.5 V; VA- = -2.5 V; VD = +3.3 V
Description
The CS5371A and CS5372A are one- and two-channel,
high-dynamic-range, fourth-order ΔΣ modulators intend-
ed for geophysical and sonar applications. When
combined with CS3301A / CS3302A differential amplifi-
ers, the CS4373A test DAC and CS5376A digital filter, a
small, low-power, self-testing, high-accuracy, multi-
channel measurement system results.
The modulators have high dynamic range and low total
harmonic distortion with very low power consumption.
They convert differential analog input signals from the
CS3301A / CS3302A amplifiers to an oversampled seri-
al bit stream at 512 kbits per second. This oversampled
bit stream is then decimated by the CS5376A digital filter
to a 24-bit output at the selected output word rate.
In normal operation, power consumption is 5 mA per
channel. Each modulator can be independently powered
down to 500 µA per channel, and by halting the input
clock they will enter a micro-power state using only 2 µA
per channel.
The CS5371A and CS5372A modulators are available in
small 24-pin SSOP packages, providing exceptional per-
formance in a very small footprint.
ORDERING INFORMATION
See page 30.
Clock
Generator
INF1+
VREF+
VREF-
VA+
VA-
VD
GND
PWDN1
MFLAG1
MDATA1
MCLK
MSYNC
MFLAG2
MDATA2
PWDN2
INF1-
INR1-
INR1+
INF2+
INF2-
INR2-
INR2+
4th Order
ΔΣ Modulator
4th Order
ΔΣ Modulator
OFST
CS5372A
Clock
Generator
INF+
VREF+
VREF-
VA+
VA-
VD
GND
PWDN
MFLAG
MDATA
MCLK
MSYNC
INF-
INR-
INR+
4th Order
ΔΣ Modulator
OFST
CS5371A
SEP ‘10
DS748F3
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Sommario

Pagina 1 - Modulators

Copyright  Cirrus Logic, Inc. 2010(All Rights Reserved)http://www.cirrus.comCS5371ACS5372ALow-power, High-performance ΔΣ ModulatorsFeatures Fourth-o

Pagina 2

CS5371A CS5372A10 DS748F3DIGITAL CHARACTERISTICS (CONT.)Notes: 20. MCLK is generated by the digital filter. If MCLK is disabled, the device automatica

Pagina 3

CS5371A CS5372ADS748F3 11DIGITAL CHARACTERISTICS (CONT.) MCLKMSYNCtMDATATDATA0(2.048 MHz)(512 kHz)(256 kHz)SYNCMFLAGFigure 6. System Timing Diagram

Pagina 4

CS5371A CS5372A12 DS748F3POWER SUPPLY CHARACTERISTICS Notes: 23. All outputs unloaded. Digital inputs forced to VD or GND respectively.24. Power suppl

Pagina 5

CS5371A CS5372ADS748F3 132. SYSTEM DIAGRAM CS5372AΔΣ ModulatorINF+INR+INF-INR-INF-INR-INF+INR+VREF+VREF-VA+VA-VDGNDMDATA1MFLAG1MDATA2MFLAG2MCLKMSYN

Pagina 6

CS5371A CS5372A14 DS748F33. MODULATOR OPERATIONThe CS5371A and CS5372A are one- andtwo-channel, fourth-order ΔΣ modulators opti-mized for extremely hi

Pagina 7

CS5371A CS5372ADS748F3 153.2 Decimated 24-bit OutputWhen the CS5371A and CS5372A modulatoroperates with the CS5376A digital filter, the fi-nal decimat

Pagina 8

CS5371A CS5372A16 DS748F34. ANALOG SIGNALSThe CS5371A and CS5372A modulators havedifferential analog inputs which are separatedinto rough and fine cha

Pagina 9

CS5371A CS5372ADS748F3 174.3 Anti-alias FilterThe modulator inputs are required to be band-width limited to ensure modulator loop stabilityand prevent

Pagina 10 - CS5371A CS5372A

CS5371A CS5372A18 DS748F35. DIGITAL SIGNALSThe CS5371A and CS5372A modulators aredesigned to operate with the CS5376A digitalfilter. The digital filte

Pagina 11

CS5371A CS5372ADS748F3 19The CS5371A and CS5372A MSYNC input isrising-edge triggered and resets the internalMCLK counter/divider to guarantee synchro-

Pagina 12

CS5371A CS5372A2 DS748F3TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ...

Pagina 13

CS5371A CS5372A20 DS748F36. POWER MODESThe CS5371A and CS5372A modulators havethree power modes. Normal operation, powerdown with MCLK enabled, and po

Pagina 14

CS5371A CS5372ADS748F3 217. VOLTAGE REFERENCEThe CS5371A and CS5372A modulators re-quire a 2.500 V precision voltage reference tobe supplied to the VR

Pagina 15

CS5371A CS5372A22 DS748F3age reference input impedance will vary withMCLK.The voltage reference external RC filter seriesresistor creates a voltage di

Pagina 16

CS5371A CS5372ADS748F3 238. POWER SUPPLIESThe CS5371A and CS5372A modulators havea positive analog power supply pin (VA+), anegative analog power supp

Pagina 17

CS5371A CS5372A24 DS748F38.4 SCR Latch-up ConsiderationsIt is recommended to connect the VA- powersupply to system ground (GND) with a re-verse-biased

Pagina 18

CS5371A CS5372ADS748F3 259. PIN DESCRIPTION - CS5371APower SuppliesVA+ _ Positive Analog Power Supply, pin 8VA- _ Negative Analog Power Supply, pin 7

Pagina 19

CS5371A CS5372A26 DS748F3VREF+ _ Positive Voltage Reference Input, pin 5Input for an external +2.500 V voltage reference relative to VREF-.VREF- _ Neg

Pagina 20

CS5371A CS5372ADS748F3 2710. PIN DESCRIPTION - CS5372APower SuppliesVA+ _ Positive Analog Power Supply, pin 8VA- _ Negative Analog Power Supply, pin 7

Pagina 21

CS5371A CS5372A28 DS748F3VREF+ _ Positive Voltage Reference Input, pin 5Input for an external +2.5 V voltage reference relative to VREF-.VREF- _ Negat

Pagina 22

CS5371A CS5372ADS748F3 2911.PACKAGE DIMENSIONSNotes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do inclu

Pagina 23

CS5371A CS5372ADS748F3 3LIST OF FIGURESFigure 1. Anti-alias Filter Components...

Pagina 24

CS5371A CS5372A30 DS748F312. ORDERING INFORMATION Model Temperature PackageCS5371A-ISZ (lead free)-40 to +85 °C 24-pin SSOPCS5372A-ISZ (lead free)

Pagina 25

CS5371A CS5372ADS748F3 3113.ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATION* MSL (Moisture Sensitivity Level) as specified by IPC/JEDEC J-STD

Pagina 26

CS5371A CS5372A32 DS748F314.REVISION HISTORY Revision Date ChangesPP1 OCT 2006 Preliminary release.F1 DEC 2006 Updated to final status with most-recen

Pagina 27

CS5371A CS5372A4 DS748F31. CHARACTERISTICS AND SPECIFICATIONS• Min / Max characteristics and specifications are guaranteed over the Specified Operatin

Pagina 28

CS5371A CS5372ADS748F3 5TEMPERATURE CONDITIONSANALOG INPUT CHARACTERISTICS Notes: 7. Maximum integrated noise over the measurement bandwidth for the

Pagina 29

CS5371A CS5372A6 DS748F3PERFORMANCE CHARACTERISTICSNotes: 9. Guaranteed by design and/or characterization.10. The upper bandwidth limit is determined

Pagina 30

CS5371A CS5372ADS748F3 7PERFORMANCE CHARACTERISTICS (CONT.)Notes: 16. Specification is for the parameter over the specified temperature range and is f

Pagina 31

CS5371A CS5372A8 DS748F3PERFORMANCE PLOTSFigure 2. Modulator Noise PerformanceFigure 3. Modulator + CS4373A Test DAC Dynamic Performance

Pagina 32

CS5371A CS5372ADS748F3 9DIGITAL CHARACTERISTICSNotes: 19. Device is intended to be driven with CMOS logic levels. Parameter Symbol Min Typ Max UnitDi

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