Cirrus-logic CS61880 Manuale Utente

Preliminary Product InformationThis document contains information for a new product.Cirrus Logic reserves the right to modify this product without not

CS6188010 DS450PP33.2 ControlSYMBOL LQFP FBGA TYPE DESCRIPTIONMCLK 10 E1 IMaster Clock InputThis pin is a free running reference clock that should be

CS61880DS450PP3 11MUX/BITSEN0 43 K2 IMultiplexed Interface/Bits Clock SelectHost Mode -This pin configures the microprocessor inter-face for multiplex

CS6188012 DS450PP3WR/DS/SDI 84 J14 IWrite Enable/Data Strobe/Serial DataIntel Parallel Host Mode - This pin, “WR”, functions as a write enable.Motorol

CS61880DS450PP3 13INTL/MOT/CODEN 88 H12 IIntel/Motorola/Coder Mode Select InputParallel Host Mode - When this pin is “Low” the micropro-cessor interfa

CS6188014 DS450PP33.3 Address Inputs/LoopbacksSYMBOL LQFP FBGA TYPE DESCRIPTIONA4 12 F4 IAddress Selector InputParallel Host Mode - During non-multip

CS61880DS450PP3 153.4 Cable Select3.5 StatusSYMBOL LQFP FBGA TYPE DESCRIPTIONCBLSEL 93 G13 ICable Impedance SelectHost Mode - The input voltage to t

CS6188016 DS450PP33.6 Digital Rx/Tx Data I/OSYMBOL LQFP FBGA TYPE DESCRIPTIONTCLK0 36 N1 ITransmit Clock Input Port 0- When TCLK is active, the TPOS

CS61880DS450PP3 17RCLK0 39 P1 OReceive Clock Output Port 0- When MCLK is active, this pin outputs the recovered clock from the signal input on RTIP an

CS6188018 DS450PP3RCLK2 78 M14 O Receive Clock Output Port 2RPOS2/RDATA2 77 M13 O Receive Positive Pulse/ Receive Data Output Port 2RNEG2/BPV2 76 M12

CS61880DS450PP3 193.7 Analog RX/TX Data I/ORCLK7 143 A1 O Receive Clock Output Port 7RPOS7/RDATA7 142 A2 O Receive Positive Pulse/ Receive Data Outpu

CS618802 DS450PP3TABLE OF CONTENTS1. PIN OUT - 144-PIN LQFP PACKAGE ...

CS6188020 DS450PP3TRING2 58 M10 O Transmit Ring Output Port 2RTIP2 60 M8 I Receive Tip Input Port 2RRING2 61 L8 I Receive Ring Input Port 2TTIP3 64 N1

CS61880DS450PP3 213.8 JTAG Test Interface3.9 MiscellaneousSYMBOL LQFP FBGA TYPE DESCRIPTIONTRST95 G12 IJTAG ResetThis active Low input resets the JT

CS6188022 DS450PP34. OPERATIONThe CS61880 is a full featured line interface unitfor up to eight E1 75 Ω or E1 120 Ω lines. The de-vice provides an in

CS61880DS450PP3 238. BUILDING INTEGRATED TIMING SYSTEMS (BITS) CLOCK MODEThis mode is used to enable one or more channelsas a stand-alone timing reco

CS6188024 DS450PP39. TRANSMITTERThe CS61880 contains eight identical transmittersthat each use a low power matched impedance driv-er to eliminate the

CS61880DS450PP3 25TNEG/UBS “High” for more than 16 TCLK cy-cles. Transmit data is input to the part via theTPOS/TDATA pin on the falling edge of TCLK.

CS6188026 DS450PP310. RECEIVERThe CS61880 contains eight identical receivers thatutilize an internal matched impedance techniquethat provides for the

CS61880DS450PP3 2710.4 Receiver Powerdown/High-ZAll eight receivers are powered down when MCLKis held low. In addition, this will force the RCLK,RPOS

CS6188028 DS450PP311. JITTER ATTENUATORThe CS61880 internal jitter attenuators can beswitched into either the receive or transmit paths.Alternatively

CS61880DS450PP3 2912. OPERATIONAL SUMMARYA brief summary of the CS61880 operations in hardware and host mode is provided in Table 8.12.1 LoopbacksTh

CS61880DS450PP3 310. RECEIVER ...

CS6188030 DS450PP312.3 Digital LoopbackDigital Loopback causes the TCLK, TPOS, andTNEG (or TDATA) inputs to be looped backthrough the jitter attenuat

CS61880DS450PP3 31EncoderDecoderTNEGTCLKRNEGRCLKTPOSRPOSTTIPTRINGRTIPRRINGClock Recovery &Data RecoveryTransmitControl &Pulse ShaperJitterAtte

CS6188032 DS450PP313. HOST MODEHost mode allows the CS61880 to be configuredand monitored using an internal register set. (Referto Table 1, “Operati

CS61880DS450PP3 33bidirectional I/O port, SDI and SDO may be tied to-gether.As illustrated in Figure 12, the ACB consists of aR/W bit, address field,

CS6188034 DS450PP313.4 Register SetThe register set available during host mode opera-tions are presented in Table 10. While the upperthree bits of th

CS61880DS450PP3 3514. REGISTER DESCRIPTIONS14.1 Revision/IDcode Register (00h)14.2 Analog Loopback Register (01h)14.3 Remote Loopback Register (02

CS6188036 DS450PP314.7 LOS Interrupt Enable Register (06h)14.8 DFM Interrupt Enable Register (07h)14.9 LOS Interrupt Status Register (08h)14.10 DF

CS61880DS450PP3 3714.14 LOS/AIS Mode Enable Register (0Dh)14.15 Automatic TAOS Register (0Eh)14.16 Global Control Register (0Fh)BIT NAME Descriptio

CS6188038 DS450PP314.17 Line Length Channel ID Register (10h)14.18 Line Length Data Register (11h)14.19 Output Disable Register (12h)14.20 AIS Sta

CS61880DS450PP3 3914.21 AIS Interrupt Enable Register (14h)14.22 AIS Interrupt Status Register (15h)14.23 AWG Broadcast Register (16h)14.24 AWG Ph

CS618804 DS450PP314.33.2 Interrupt Status Registers ... 4115. ARBITRARY

CS6188040 DS450PP314.26 AWG Enable Register (19h)14.27 Reserved Register (1Ah)14.28 Reserved Register (1Bh)14.29 Reserved Register (1Ch)14.30 Res

CS61880DS450PP3 4114.33.1 Interrupt Enable RegistersThe Interrupt Enable registers: LOS Interrupt En-able Register (06h) (See Section 14.7 on page 36

CS6188042 DS450PP315. ARBITRARY WAVEFORM GENERATORUsing the Arbitrary Waveform Generator (AWG)allows the user to customize the transmit pulseshapes t

CS61880DS450PP3 43sample address (00000 binary) needs to be writtento the AWG Phase Address Register (17h) (SeeSection 14.24 on page 39), and each sub

CS6188044 DS450PP316.1 TAP ControllerThe TAP Controller is a 16 state synchronous statemachine clocked by the rising edge of TCK. TheTMS input govern

CS61880DS450PP3 4516.1.8 Pause-DR The pause state allows the test controller to tempo-rarily halt the shifting of data through the currenttest data r

CS6188046 DS450PP316.1.14 Exit1-IR This is a temporary state. The test data register se-lected by the current instruction retains its previousvalue.1

CS61880DS450PP3 4716.3 Device ID Register (IDR)Revision section: 0h = Rev A, 1h = Rev B and so on. The device Identification Code [27 - 12] is derive

CS6188048 DS450PP328 LOOP1/D1 I LPI129 LOOP1/D1 O LPO130 LOOP2/D2 I LPT231 LOOP2/D2 I LPI232 LOOP2/D2 O LPO233 LOOP3/D3 I LPT334 LOOP3/D3 I LPI335 LOO

CS61880DS450PP3 49Notes:1) LPOEN controls the LOOP[7:0] pins. Setting LPOEN to “1” configures LOOP[7:0] as outputs. The output value drivenon the pins

CS61880DS450PP3 5LIST OF FIGURESFigure 1. CS61880 144-Pin LQFP Package Pin Outs ... 7

CS6188050 DS450PP318. APPLICATIONSFigure 16. Internal RX/TX Impedance Matching+RGND+3.3VRV+T1 1:2REFCS61880One ChannelTRINGTTIPTRANSMITLINET2 1:1.15

CS61880DS450PP3 51Figure 17. Internal TX, External RX Impedance Matching+RGND0.1µF+3.3VRV+T1 1:2REFTRINGTTIPT2 1:1.15RTIPRRINGR1R213.3kΩGNDCBLSELTV+V

CS6188052 DS450PP318.1 Transformer SpecificationsRecommended transformer specifications areshown in Table 15. Any transformer used with theCS61880 sh

CS61880DS450PP3 5319. CHARACTERISTICS AND SPECIFICATIONS19.1 Absolute Maximum RatingsCAUTION: Operations at or beyond these limits may result in per

CS6188054 DS450PP319.3 Digital Characteristics(TA = -40° C to 85° C; TV+, RV+ = 3.3 V ±5%; GND = 0 V)19.4 Transmitter Analog Characteristics (TA = -

CS61880DS450PP3 5519.5 Receiver Analog Characteristics(TA = -40° C to 85° C; TV+, RV+ = 3.3 V ±5%; GND = 0 V)) Notes: 10. Parameters guaranteed by de

CS6188056 DS450PP319.6 Jitter Attenuator Characteristics(TA = -40° C to 85° C; TV+, RV+ = 3.3 V ±5%; GND = 0 V)Notes: 17. Attenuation measured with s

CS61880DS450PP3 57PEAK TO PEAK JITTER (UI)FREQUENCY IN Hz110 1k100 100k1.8 4.9 20 300 10k2.4k 18k1.110100.2.41.510001828138300ITU G.823TYP. E1 Perform

CS6188058 DS450PP319.7 Master Clock Switching Characteristics19.8 Transmit Switching Characteristics19.9 Receive Switching CharacteristicsNotes: 19

CS61880DS450PP3 59RCLKtsuRPOS/RNEGCLKE = 1tsuththRPOS/RNEGCLKE = 0Figure 20. Recovered Clock and Data Switching CharacteristicsTPOS/TNEGTCLKtpw2tpwh2

CS618806 DS450PP3LIST OF TABLESTable 1. Operation Mode Selection...

CS6188060 DS450PP319.10 Switching Characteristics - Serial PortNotes: 21. If SPOL = 0, then CS should return high no sooner than 20 ns after the 16th

CS61880DS450PP3 6119.11 Switching Characteristics - Parallel Port (Multiplexed Mode) Parameter Ref. # Min. Typ. Max UnitPulse Widt

CS6188062 DS450PP3ALEWRD[7:0]RDYHIGH-ZHIGH-ZCS112 47698352131514ADDRESS Write DataFigure 25. Parallel Port Timing - Write; Intel® Multiplexed Address

CS61880DS450PP3 63D[7:0]R/WDSASWrite DataHIGH-Z HIGH-ZADDRESS1524316171876CS8129ACKFigure 27. Parallel Port Timing - Write; Motorola® Multiplexed Add

CS6188064 DS450PP319.12 Switching Characteristics- Parallel Port (Non-Multiplexed Mode) Parameter Ref. # Min. Typ. Max UnitAd

CS61880DS450PP3 65A[4:0]D[7:0]ALERDYWR(pulled high)CSHIGH-Z1710HIGH-Z11 1225346ADDRESSWrite DataFigure 29. Parallel Port Timing - Write; Intel Non-Mu

CS6188066 DS450PP3(pulled high)HIGH-Z1713HIGH-Z1415253 46ADDRESSWrite DataACKD[7:0]CSR/WDSASA[4:0]Figure 31. Parallel Port Timing - Write; Motorola N

CS61880DS450PP3 6719.13 Switching Characteristics - JTAGParameter Symbol Min. Max UnitsCycle Time tcyc200 - nsTMS/TDI to TCK Rising Setup Time tsu50

CS6188068 DS450PP320. COMPLIANT RECOMMENDATIONS AND SPECIFICATIONS ETSI ETS 300-011ETSI ETS 300-166ETSI ETS 300-233ETSI TBR 12/13IEEE 1149.1ITU-T I.4

CS61880DS450PP3 6921. 160-BALL FBGA PACKAGE DIMENSIONSFigure 34. 160-Ball FBGA Package Drawing

CS61880DS450PP3 71. PIN OUT - 144-PIN LQFP PACKAGE 144143142140139138137136135141134133132131130129128127126125124123122121120CS61880144-PinLQFP373

CS6188070 DS450PP322. 144-PIN LQFP PACKAGE DIMENSIONS Table 16. 144-Pin Package DimensionsINCHES MILLIMETERSDIM MIN NOM MAX MIN NOM MAXA --- 0.5

CS618808 DS450PP32. PIN OUT - 160-BALL FBGA PACKAGE1234567891011121314CLKETDOCBLSELREFTPOS5RPOS4TPOS4RPOS5TPOS2RPOS3TPOS3RPOS2TTIP5TRING4TTIP4TRING5T

CS61880DS450PP3 93. PIN DESCRIPTIONS3.1 Power SuppliesSYMBOL LQFP FBGA TYPE DESCRIPTIONVCCIO1792G1G14Power Supply, Digital Interface: Power supply f