Cirrus-logic CS5530 Manuale Utente

Copyright  Cirrus Logic, Inc. 2009(All Rights Reserved)http://www.cirrus.comCS553024-bit ADC with Ultra-low-noise AmplifierFeatures & Description

CS553010 DS742F3CSSCLKMSBMSB-1LSBSDIt3t6t4 t5 t1t2Figure 1. SDI Write Timing (Not to Scale)CSSCLKMSB MSB-1LSBSDOt7t9t8t1t2Figure 2. SDO Read Timing

CS5530DS742F3 112. GENERAL DESCRIPTIONThe CS5530 is a ΔΣ Analog-to-Digital Converter(ADC) which uses charge-balance techniques toachieve 24-bit perfo

CS553012 DS742F32.1.1 Analog Input SpanThe full-scale input signal that the converter can dig-itize is a function of the reference voltage connectedb

CS5530DS742F3 13initialization sequence, the user must also performa system reset sequence which is as follows: Writea logic 1 into the RS bit of the

CS553014 DS742F32.2.2 Command Register DescriptionsREAD/WRITE OFFSET REGISTERR/W (Read/Write)0 Write offset register.1 Read offset register.READ/WRIT

CS5530DS742F3 15SYNC0Function: End of the serial port re-initialization sequence.NULLFunction:This command is used to clear a port flag and keep the c

CS553016 DS742F32.2.3 Serial Port InterfaceThe CS5530’s serial interface consists of four con-trol lines: CS, SDI, SDO, SCLK. Figure 7 detailsthe com

CS5530DS742F3 172.2.4 Reading/Writing On-Chip RegistersThe CS5530’s offset, gain, and configuration regis-ters are readable and writable while the co

CS553018 DS742F3the magnitude of the reference voltage to achieveoptimal performance. Figures 8 and 9 model the ef-fects on the reference’s input impe

CS5530DS742F3 192.3.10 Configuration Register Description PSS (Power Save Select)[31]0 Standby Mode (Oscillator active, allows quick power-up).1 Slee

CS55302 DS742F3TABLE OF CONTENTS1. CHARACTERISTICS AND SPECIFICATIONS ... 4ANALOG CHARAC

CS553020 DS742F3WR3-WR0 (Word Rate) [14:11] The listed Word Rates are for continuous conversion mode using a 4.9152 MHz clock. All word rates will sca

CS5530DS742F3 212.4 CalibrationCalibration is used to set the zero and gain slope ofthe ADC’s transfer function. The CS5530 providessystem calibratio

CS553022 DS742F32.4.4 Performing CalibrationsTo perform a calibration, the user must send a com-mand byte with its MSB=1, and the appropriatecalibrat

CS5530DS742F3 23For maximum accuracy, calibrations should be per-formed for both offset and gain. When the device is used without calibration, theunca

CS553024 DS742F32.5.2 Continuous Conversion ModeWhen the user transmits the perform continuousconversion command, the converter begins contin-uous co

CS5530DS742F3 252.6 Using Multiple ADCs SynchronouslySome applications require synchronous data out-puts from multiple ADCs converting different ana-

CS553026 DS742F32.7.1 Conversion Data Output DescriptionsCS5530 (24-BIT CONVERSIONS) Conversion Data Bits [31:8]These bits depict the latest output c

CS5530DS742F3 272.8 Digital FilterThe CS5530 has a linear phase digital filter whichis programmed to achieve a range of output wordrates (OWRs) as st

CS553028 DS742F32.9 Clock GeneratorThe CS5530 includes an on-chip inverting amplifi-er which can be connected with an external crystalto provide the

CS5530DS742F3 29OSC2VD+VA+VREF+VREF-DGNDVA -AIN1+SDISCLKSDOCS5530OSC1CS10 Ω+5 VAnalogSupply0.1 µF0.1 µF+-17312AIN1-51591013111214166OptionalClockSourc

CS5530DS742F3 3LIST OF FIGURESFigure 1. SDI Write Timing (Not to Scale)...

CS553030 DS742F3OSC2VD+VA+VREF+VREF-DGNDVA -AIN1+SDISCLKSDOCS5530OSC1CS10 Ω+3 VAnalogSupply0.1 µF0.1 µF+-17312AIN1-51591013111214166OptionalClockSourc

CS5530DS742F3 312.11 Getting StartedThis A/D converter has several features. From asoftware programmer’s prospective, what shouldbe done first? To be

CS553032 DS742F33. PIN DESCRIPTIONS Clock GeneratorOSC1; OSC2 – Master ClockAn inverting amplifier inside the chip is connected between these pins an

CS5530DS742F3 33Measurement and Reference InputsAIN1+, AIN1- – Differential Analog Input Differential input pins into the device.VREF+, VREF- – Voltag

CS553034 DS742F35. PACKAGE DRAWINGSNotes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but do include mold mi

CS5530DS742F3 356. ORDERING INFORMATION 7. ENVIRONMENTAL, MANUFACTURING, & HANDLING INFORMATIONModel Number Bits Channels Linearity Error (Max)

CS553036 DS742F3Revision HistoryREVISION DATE CHANGESA1 OCT 2006 Advance ReleaseA2 NOV 2006 Updated power consumption values.A3 NOV 2006 Updated noise

CS55304 DS742F31. CHARACTERISTICS AND SPECIFICATIONSANALOG CHARCTERISTICS (VA+, VD+ = 5 V ±5%; VREF+ = 5 V; VA-, VREF-, DGND = 0 V; MCLK = 4.9152 MH

CS5530DS742F3 5ANALOG CHARACTERISTICS (Continued) (See Notes 1 and 2.) Notes: 5. See the section of the data sheet which discusses input models.6. In

CS55306 DS742F3ANALOG CHARACTERISTICS (Continued) (See Notes 1 and 2.)7. All outputs unloaded. All input CMOS levels.8. Tested with 100 mV change on

CS5530DS742F3 75 V DIGITAL CHARACTERISTICS (VA+, VD+ = 5 V ±5%; VA-, DGND = 0 V; See Notes 2 and 11.)3 V DIGITAL CHARACTERISTICS (TA = 25 °C; VA+ = 5V

CS55308 DS742F3DYNAMIC CHARACTERISTICS 12. The ADCs use a Sinc5 filter for the 3200 Sps and 3840 Sps output word rate (OWR) and a Sinc5 filter followe

CS5530DS742F3 9SWITCHING CHARACTERISTICS (VA+ = 2.5 V or 5 V ±5%; VA- = -2.5V±5% or 0 V; VD+ = 3.0 V ±10% or 5 V ±5%;DGND = 0 V; Levels: Logic 0 = 0 V