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DS732UM10 Copyright 2010 Cirrus Logic, Inc 9-28
Pin Assignments
CS4953xx Hardware User’s Manual
137 29 DAI1_SCLK
PCM Audio Input Bit
Clock
DSD_CLK DSD Audio Input Clock
3.3V
(5V tol)
In Y
138 30 DAI1_LRCLK
PCM Audio Input
Sample Rate (Left/
Right) Clock
DSD4 DSD Audio Input Data 4
3.3V
(5V tol)
In Y
139 31 GNDIO8 I/O ground 0V PWR
140 - GPIO42
General Purpose
Input/Output
1. DAI2_LRCLK
2. BDI_REQ
3. PCP_IRQ
4. PCP_BSY
1.PCM Audio Input Sample
Rate Clock
2. Bursty Data Input Request
3. Parallel Control Port Data
Ready Interrupt Request
4. Parallel Control Port Input
Busy
3.3V
(5V tol)
BiDir/
OD
IN Y
-32GPIO42
General Purpose
Input/Output
1. DAI2_LRCLK
2. BDI_REQ
1.PCM Audio Input Sample
Rate Clock
2. Bursty Data Input Request
3.3V
(5V tol)
BiDir/
OD
IN Y
141 33 GPIO43
General Purpose
Input/Output
1. DAI2_SCLK
2. BDI_CLK
1.PCM Audio Input Bit Clock
2. Bursty Data Input Bit Clock
3.3V
(5V tol)
BiDir IN Y
142 34 DAI2_DATA PCM Audio Input Data
1. DAI1_DATA4
2. DSD5
3. BDI_DATA
1. PCM Audio Input Data 4
2. DSD Audio Input Data 5
3. Bursty Data Input Data
3.3V
(5V tol)
In Y
143 - GPIO27
General Purpose
Input/Output
3.3V
(5V tol)
BiDir IN Y
144 - GPIO26
General Purpose
Input/Output
3.3V
(5V tol)
BiDir IN Y
-35GPIO26
General Purpose
Input/Output
1. DAO2_DATA3
2. XMTB
3. UART_TX_ENABLE
1. Digital Audio Output 3.
2. Outputs IEC60958/61937
format bi-phase mark encoded
S/PDIF data
3. Enable the UART_TX pin
3.3V
(5V tol)
BiDir IN Y
Table 9-10. Pin Assignments (Continued)
LQFP-
144
Pin #
LQFP-
128
Pin #
Function 1
(Default)
Description of Default
Function
Secondary Functions Description of Secondary
Functions
Pwr Type
Reset
State
Pullup
at
Reset
- CS4953xx 1
- Contents 3
- Chapter 1 9
- Introduction 9
- 1.1 Overview 9
- 1.2.1 DSP Core 11
- 1.2.3 Debug Controller (DBC) 11
- 1.2.11 SDRAM Controller 13
- 1.2.12 Flash Controller 13
- 1.2.13 DMA Controller 13
- 1.2.14 Timers 13
- 1.2.15 Clock Manager and PLL 14
- Chapter 2 15
- Operational Modes 15
- 2.1 Overview 15
- Master Boot 16
- 2.3 Slave Boot Procedures 18
- Slave Boot Procedures 19
- 2.3.2 Slave Boot 21
- 2.3.3 Boot Messages 24
- 2.3.3.5 Soft Reset 26
- Master Boot Procedure 27
- 2.5 Softboot 28
- 2.5.2 Softboot Procedure 29
- 2.5.2.2 Softboot Example 30
- Softboot 31
- Chapter 3 33
- Serial Control Port 33
- 3.1 Overview 33
- 3.3.1 I 34
- C System Bus Description 34
- 3.3.2 I 36
- C Bus Dynamics 36
- I2C Port 37
- Figure 3-4. I 37
- C Address with ACK and NACK 37
- 3.3.3 I 39
- C Messaging 39
- Figure 3-8. I 40
- C Write Flow Diagram 40
- 3.3.3.3 I 41
- C Write Protocol 41
- Figure 3-9. I 42
- C Read Flow Diagram 42
- 3.3.3.5 I 43
- C Read Procedure 43
- Note: The I 44
- 3.4 SPI Port 45
- SPI Port 46
- 3.4.2 SPI Bus Dynamics 47
- 3.4.3 SPI Messaging 48
- 3.4.3.2 SPI Write Protocol 49
- Parallel Control Availability 55
- 5.1.1 DAI Pin Description 57
- 5.1.3 BDI Port 59
- 5.1.4 Digital Audio Formats 60
- DAI Hardware Configuration 61
- Chapter 6 65
- DSD Input 65
- Chapter 7 67
- Figure 7-2. I 69
- OUTPUT A B C D E F 70
- 7.1.5 S/PDIF Transmitter 77
- Description Hex Message 78
- SDRAM Controller 79
- Flash Memory Controller 80
- Mnemonic Hex Message 83
- Typical Connection Diagrams 89
- Figure 9-1. LQFP-144, I 90
- Figure 9-4. LQFP-144, I 93
- Figure 9-6. LQFP-128, I 95
- Pin Description 98
- Table 9-1. Core Supply Pins 98
- Table 9-2. I/O Supply Pins 98
- Table 9-4. PLL Supply Pins 99
- Clocking 100
- Table 9-5. PLL Filter Pins 100
- 9.4.1 Operational Mode 101
- Table 9-8. Reset Pin 102
- 144-Pin LQFP Pin Assigments 103
- 128-Pin LQFP Pin Assigments 104
- the 128-Pin LQFP Pin Layout 104
- Table 9-10. Pin Assignments 105
- Pin Assignments 106
- Revision History 117
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