Cirrus-logic CS2100-OTP Manuale Utente

Copyright  Cirrus Logic, Inc. 2010(All Rights Reserved)http://www.cirrus.comFractional-N Clock MultiplierFeatures Clock Multiplier / Jitter Reductio

CS2100-OTP10 DS841F2 Figure 6. Hybrid Analog-Digital PLLNDigital FilterFrequency Comparator forFrac-N GenerationFrequency Reference Clock Delta-Sigm

CS2100-OTPDS841F2 115. APPLICATIONS5.1 One Time ProgrammabilityThe one time programmable (OTP) circuitry in the CS2100-OTP allows for pre-configuratio

CS2100-OTP12 DS841F2example of how to determine the range of RefClk frequencies around 12 MHz to be used in order toachieve the lowest jitter PLL outp

CS2100-OTPDS841F2 13clock (SysClk). This allows the low-jitter timing reference clock to be used as the clock which the FrequencySynthesizer multiplie

CS2100-OTP14 DS841F2While acquiring lock, the digital loop bandwidth is automatically set to a large value. Once lock isachieved, the digital loop ban

CS2100-OTPDS841F2 155.4.2 Ratio Modifier (R-Mod)The Ratio Modifier is used to internally multiply/divide the currently addressed RUD (Ratio0-3 stored

CS2100-OTP16 DS841F2final calculation used to determine the output to input clock ratio. The effective ratio is then corrected forthe internal divider

CS2100-OTPDS841F2 175.6 Auxiliary OutputThe auxiliary output pin (AUX_OUT) can be mapped, as shown in Figure 14, to one of four signals: refer-ence cl

CS2100-OTP18 DS841F25.7.2 M2 Mode Pin FunctionalityM2 usage is mapped to one of the optional special functions via the M2Config[2:0] global parameter.

CS2100-OTPDS841F2 195.8 Clock Output Stability Considerations5.8.1 Output SwitchingThe CS2100-OTP is designed such that re-configuration of the clock

CS2100-OTPDS841F2 2TABLE OF CONTENTS1. PIN DESCRIPTION ...

CS2100-OTP20 DS841F26. PARAMETER DESCRIPTIONSAs mentioned in Section 5.1 on page 11, there are two different kinds of parameter configuration sets, Mo

CS2100-OTPDS841F2 216.1.2 Auxiliary Output Source Selection (AuxOutSrc[1:0])Selects the source of the AUX_OUT signal.Note: When set to 11, the AuxLock

CS2100-OTP22 DS841F26.3.3 Enable PLL Clock Output on Unlock (ClkOutUnl)Defines the state of the PLL output during the PLL unlock condition.6.3.4 Low-F

CS2100-OTPDS841F2 237. CALCULATING THE USER DEFINED RATIONote: The software for use with the evaluation kit has built in tools to aid in calculating a

CS2100-OTP24 DS841F28. PROGRAMMING INFORMATIONField programming of the CS2100-OTP is achieved using the hardware and software tools included with theC

CS2100-OTPDS841F2 259. PACKAGE DIMENSIONSNotes: 1. Reference document: JEDEC MO-1872. D does not include mold flash or protrusions which is 0.15 mm ma

CS2100-OTP26 DS841F210.ORDERING INFORMATIONThe CS2100-OTP is ordered as an un-programmed device. The CS2100-OTP can also be factory programmed forlarg

CS2100-OTPDS841F2 39. PACKAGE DIMENSIONS ...

CS2100-OTP4 DS841F21. PIN DESCRIPTIONPin Name # Pin DescriptionVD 1 Digital Power (Input) - Positive power supply for the digital and analog sections.

CS2100-OTPDS841F2 52. TYPICAL CONNECTION DIAGRAM 21GNDM2M1XTI/REF_CLKFrequency Reference CLK_INXTOCLK_OUTAUX_OUT0.1 µFVD+3.3 VM0Low-JitterTiming Ref

CS2100-OTP6 DS841F23. CHARACTERISTICS AND SPECIFICATIONS RECOMMENDED OPERATING CONDITIONSGND = 0 V; all voltages with respect to ground. (Note 1)Notes

CS2100-OTPDS841F2 7AC ELECTRICAL CHARACTERISTICSTest Conditions (unless otherwise specified): VD = 3.1 V to 3.5 V; TA = -10°C to +70°C (Commercial Gra

CS2100-OTP8 DS841F2PLL PERFORMANCE PLOTSTest Conditions (unless otherwise specified): VD = 3.3 V; TA=25°C; CL=15pF; fCLK_OUT= 12.288 MHz; fCLK_IN= 12.

CS2100-OTPDS841F2 94. ARCHITECTURE OVERVIEW4.1 Delta-Sigma Fractional-N Frequency SynthesizerThe core of the CS2100 is a Delta-Sigma Fractional-N Freq