Cirrus-logic CDB48500-USB Manuale Utente Scaricare il pdf (Pagina 22)

3.1.11.3 Clock and Data Flow for CDB USB Master Card Source

Figure 3-4. CDB USB Master Card Clocking and Data Flow

Figure 3-4 illustrates the clocking architecture used when IIS(USB) is used as an audio source, as described in

Section 4.2.2, “Changing the Audio Input Source” on page 4-3). MCLK is generated by the PLL on the USB

Master card. The PLD on the USB Master Card generates SCLK and LRCLK for the DAI side of the DSP from

the MCLK.

On the output side, the CS485xx slaves to MCLK from the USB Master Card and masters SCLK and LRCLK for

the DAC side of the CS42448.The CS485XX always masters its output clocks (DSP_SCLK/DSP_LRCLK).

§§

CS42448

CS485XX

CS42448

CDB USB

MASTER

CARD

MUXED_DSP_SCLK1

DSP_SCLK

DSP_LRCLK

MUXED_DSP_LRCLK1

MUXED_DAI[4:0]

DSP_DA01[3:0]

XMTA SPDIF OUT

MUXED_MCLK

DAI DAO

SDIN

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Cirrus-logic CDB48500-USB Manuale Utente Pagina 22