Cirrus-logic CS8415A Manuale Utente Scaricare il pdf (Pagina 45)

DS470F4 45

CS8415A

15.3.4 Jitter Attenuation

Shown in Figure 21, Figure 22, Figure 23, and Figure 24 are jitter attenuation plots for the various revi-

sions of the CS8415A when used with the appropriate external PLL component values (as noted in

Table 6). The AES3 and IEC60958-4 specifications do not have allowances for locking to sample rates

less than 32 kHz. These specifications state a maximum of 2 dB jitter gain or peaking.

−1

−20

−15

−10

−5

Jitter Frequency (Hz)

Jitter Attenuation (dB)

−1

−20

−15

−10

−5

Jitter Frequency (Hz)

Jitter Attenuation (dB)

−1

−25

−20

−15

−10

−5

Jitter Frequency (Hz)

Jitter Attenuation (dB)

−1

−25

−20

−15

−10

−5

Jitter Frequency (Hz)

Jitter Attenuation (dB)

Figure 21. Revision A Figure 22. Revision A1

Figure 23. Revision A2 using A1 Values Figure 24. Revision A2 using A2* Values

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Cirrus-logic CS8415A Manuale Utente Pagina 45