Cirrus-logic CS4365 Manuale Utente Pagina 44

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44 DS670F2
CS4365
6.12 PCM Clock Mode (address 16h)
6.12.1 Master Clock DIVIDE by 2 ENABLE (MCLKDIV)
Function:
When set to 1, the MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2
prior to all other internal circuitry.
When set to 0 (default), MCLK is unchanged.
76543210
Reserved Reserved MCLKDIV Reserved Reserved Reserved Reserved Reserved
00000000
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