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DS604F2 37
CS42426
Since the read operation cannot set the MAP, an aborted write operation is used as a preamble. As shown
in Figure 23, the write operation is aborted after the acknowledge for the MAP byte by sending a stop con-
dition. The following pseudocode illustrates an aborted write operation followed by a read operation.
Send start condition.
Send 10011xx0 (chip address & write operation).
Receive acknowledge bit.
Send MAP byte, auto increment off.
Receive acknowledge bit.
Send stop condition, aborting write.
Send start condition.
Send 10011xx1(chip address & read operation).
Receive acknowledge bit.
Receive byte, contents of selected register.
Send acknowledge bit.
Send stop condition.
Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each
byte is separated by an acknowledge bit.
4.7 Interrupts
The CS42426 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt
input pin on the host microcontroller. The INT pin may be set to be active low, active high or active low with
no active pull-up transistor. This last mode is used for active low, wired-OR hook-ups, with multiple periph-
erals connected to the microcontroller interrupt input pin.
Many conditions can cause an interrupt, as listed in the interrupt status register descriptions (see “Interrupt
Status (address 20h) (Read Only)” on page 56). Each source may be masked off through mask register bits.
In addition, each source may be set to rising edge, falling edge, or level-sensitive. Combined with the option
of level-sensitive or edge-sensitive modes within the microcontroller, many different configurations are pos-
sible, depending on the needs of the equipment designer.
SCL
CHIP ADDRESS (WRITE)
MAP BYTE
DATA
DATA +1
START
ACK
STOP
ACK
ACK
ACK
1 0 0 1 1 AD1 AD0 0
SDA
1 0 0 1 1 AD1 AD0 1
CHIP ADDRESS (READ)
START
INCR 6 5 4 3 2 1 0
7 0 7 0 7 0
NO
168 9 12 13 14 154 5 6 7 0 1 20 21 22 23 24
26 27 28
2 3 10 11 17 18 19 25
ACK
DATA + n
STOP
Figure 23. Control Port Timing, I²C Read
- Features 1
- General Description 1
- TABLE OF CONTENTS 2
- LIST OF FIGURES 3
- LIST OF TABLES 5
- ABSOLUTE MAXIMUM RATINGS 6
- ANALOG INPUT CHARACTERISTICS 7
- ANALOG OUTPUT CHARACTERISTICS 9
- SWITCHING CHARACTERISTICS 11
- FORMAT 13
- DC ELECTRICAL CHARACTERISTICS 14
- 2. PIN DESCRIPTIONS 16
- DS604F2 17 17
- 18 DS604F2 18
- DS604F2 19 19
- 4. APPLICATIONS 20
- 4.3 Analog Outputs 21
- 4.3.2 Interpolation Filter 21
- 4.3.4 ATAPI Specification 22
- 4.4 Clock Generation 23
- 4.4.2 OMCK System Clock Mode 24
- 4.4.3 Master Mode 24
- 4.4.4 Slave Mode 24
- 4.5 Digital Interfaces 25
- Left Channel 27
- Right Channel 27
- 6543210987 27
- MSB LSB MSB LSB 28
- Left Channel Right Channel 29
- ADC_SDOUT 29
- 4.5.4.1 OLM Config #1 31
- CS42416 31
- 4.5.4.2 OLM Config #2 32
- 4.5.4.3 OLM Config #3 33
- 4.5.4.4 OLM Config #4 34
- 4.6.1 SPI Mode 35
- 4.6.2 I²C Mode 36
- 4.7 Interrupts 37
- 4.8 Reset and Power-Up 38
- 5. REGISTER QUICK REFERENCE 39
- 40 DS604F2 40
- Addr Function 7 6 5 4 3 2 1 0 40
- DS604F2 41 41
- 6. REGISTER DESCRIPTION 42
- 76543210 43
- RAMP_UP RAMP_DN 51
- 7. PARAMETER DEFINITIONS 60
- 8.1 ADC Input Filter 61
- 8.2 DAC Output Filter 61
- 9. APPENDIX B: PLL FILTER 62
- 9.1.3 Circuit Board Layout 63
- 64 DS604F2 64
- DS604F2 65 65
- 65
- 66 DS604F2 66
- DS604F2 67 67
- 68 DS604F2 68
- DS604F2 69 69
- 12.PACKAGE DIMENSIONS 70
- THERMAL CHARACTERISTICS 70
- 64L LQFP PACKAGE DRAWING 70
- 13.ORDERING INFORMATION 71
- 14.REFERENCES 71
- 15.REVISION HISTORY 72
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